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a
FEATURES SNR = 54 dB with 99 MHz Analog Input 500 MHz Analog Bandwidth On-Chip Reference and Track/Hold 1.5 V p-p Differential Analog Input Range 5.0 V and 3.3 V Supply Operation 3.3 V CMOS/TTL Outputs Power: 2.1 W Typical at 210 MSPS Demultiplexed Outputs Each at 105 MSPS Output Data Format Option Data Sync Input and Data Clock Output Provided Interleaved or Parallel Data Output Option APPLICATIONS Communications and Radar Local Multipoint Distribution Service (LMDS) High-End Imaging Systems and Projectors Cable Reverse Path Point-to-Point Radio Link
REFIN
10-Bit, 210 MSPS A/D Converter AD9410
FUNCTIONAL BLOCK DIAGRAM
REFOUT AGND DGND VD VDD VCC REFERENCE
AD9410
PORT A 10 ORA D9A-D0A
AIN AIN
T/H
ADC 10-BIT CORE
10 ORB D9B-D0B
DS DS ENCODE ENCODE
PORT B TIMING AND SYNCHRONIZATION
10
DCO DCO DFS I/P
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9410 is a 10-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is optimized for high-speed conversion and ease of use. The product operates at a 210 MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires a 5.0 V and 3.3 V power supply and up to a 210 MHz differential clock input for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible, and separate output power supply pins also support interfacing with 3.3 V logic. The clock input is differential and TTL/CMOS-compatible. The 10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V) supplies. Two output buses support demultiplexed data up to 105 MSPS rates, and binary or two's complement output coding format is available. A data sync function is provided for timingdependent applications. An output clock simplifies interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data. Fabricated on an advanced BiCMOS process, the AD9410 is available in an 80-lead surface-mount plastic package (PowerQuad(R)2) specified over the industrial temperature range (-40C to +85C).
PowerQuad is a registered trademark of Amkor Electronics, Inc.
High Resolution at High Speed--The architecture is specifically designed to support conversion up to 210 MSPS with outstanding dynamic performance. Demultiplexed Output--Output data is decimated by two and provided on two data ports for ease of data transport. Output Data Clock--The AD9410 provides an output data clock synchronous with the output data, simplifying the timing between data and other logic. Data Synchronization--A DS input is provided to allow for synchronization of two or more AD9410s in a system, or to synchronize data to a specific output port in a single AD9410 system.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD9410-SPECIFICATIONS
DC SPECIFICATIONS T = 25 C; unless otherwise noted.)
A
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = -0.5 dBFS; Clock input = 210 MSPS;
Test Level
Parameter RESOLUTION DC ACCURACY No Missing Codes1 Differential Nonlinearity Integral Nonlinearity Gain Error Gain Tempco ANALOG INPUT Input Voltage Range (With Respect to AIN) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY Power Dissipation AC2 Power Dissipation DC3 IVCC3 IVD3 Power Supply Rejection Ratio PSRR
Temp
Min
Typ 10
Max
Unit Bits
Full 25C Full 25C Full 25C Full Full Full 25C Full Full Full Full 25C 25C 25C Full Full Full 25C
IV I VI I VI I V V V I VI VI V VI V V V VI VI VI I
-1.0 -1.0 -2.5 -3.0 -6.0
Guaranteed 0.5 1.65 0 130 768 3.0 +3 2.5 50 875 3 500 2.1 2.0 128 401 +0.5
+1.25 +1.5 +2.5 +3.0 +6.0
LSB LSB LSB LSB % FS ppm/C mV p-p V mV mV V ppm/C pF MHz W W mA mA mV/V
-15 -20 2.4 610
+15 +20 2.6 1250
-7.5
2.4 145 480 +7.5
NOTES 1 Package heat slug should be attached when operating at greater than 70 C ambient temperature. 2 Encode = 210 MSPS, A IN = -0.5 dBFS 10 MHz sine wave, I VDD = 31 mA typical at C LOAD = 5 pF. 3 Encode = 210 MSPS, A IN = dc, outputs not switching. Specifications subject to change without notice.
SWITCHING SPECIFICATIONS input = 210 MSPS; T = 25 C; unless otherwise noted.)
A
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = -0.5 dBFS; Clock
Test Level VI IV IV IV V V VI VI V V VI IV IV IV VI VI
Parameter SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV) Output Propagation Delay (tPD) Output Rise Time (tR) Output Fall Time (tF) CLKOUT Propagation Delay1 (tCPD) Data to DCO Skew (tPD-tCPD) DS Setup Time (tSDS) DS Hold Time (tHDS) Interleaved Mode (A, B Latency) Parallel Mode (A, B Latency)
NOTES 1 CLOAD = 5 pF. Specifications subject to change without notice.
Temp Full Full 25C 25C 25C 25C Full Full 25C 25C Full Full Full Full Full Full
Min 210
Typ
Max
Unit MSPS MSPS ns ns ns ps rms ns ns ns ns ns ns ns ns Cycles Cycles
100 1.2 1.2 2.4 2.4 1.0 0.65 7.4 1.8 1.4 4.8 1
3.0
2.6 0 0.5 0
6.4 2
A = 6, B = 6 A = 7, B = 6
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DIGITAL SPECIFICATIONS
Parameter
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = -0.5 dBFS; Clock input = 210 MSPS; TA = 25 C; unless otherwise noted.)
Temp Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Test Level IV IV V V V V IV V V IV V V VI VI Min 4 1 50 50 400 1 0.4 1.6 1.5 0.4 1.5 3 VDD - 0.05 0.05 Binary or Two's Complement Typ Max
AD9410
Unit V V A A A A V k V V V pF V V
DIGITAL INPUTS DFS, Input Logic "1" Voltage DFS, Input Logic "0" Voltage DFS, Input Logic "1" Current DFS, Input Logic "0" Current I/P Input Logic "1" Current1 I/P Input Logic "0" Current1 ENCODE, ENCODE Differential Input Voltage ENCODE, ENCODE Differential Input Resistance ENCODE, ENCODE Common-Mode Input Voltage2 DS, DS Differential Input Voltage DS, DS Common-Mode Input Voltage Digital Input Pin Capacitance DIGITAL OUTPUTS Logic "1" Voltage (VDD = 3.3 V) Logic "0" Voltage (VDD = 3.3 V) Output Coding
NOTES 1 I/P pin Logic "1" = 5 V, Logic "0" = GND. It is recommended to place a series 2.5 k ( 10%) resistor to V DD when setting to Logic "1" to limit input current. 2 See Encode Input section in Applications section. Specifications subject to change without notice.
AC SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = -0.5 dBFS; Clock input = 210 MSPS; TA = 25 C; unless otherwise noted.)
Temp 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Test Level V V I I V I I V I I V I I V I I V I I V V 52.5 52 Min Typ 2 2 55 54 53 54 53 52 8.8 8.6 8.4 -65 -63 -65 -69 -67 -62 61 60 58 58 Max Unit ns ns dB dB dB dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS
Parameter DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 82 MHz fIN = 160 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 82 MHz fIN = 160 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 82 MHz fIN = 160 MHz Second Harmonic Distortion fIN = 10.3 MHz fIN = 82 MHz fIN = 160 MHz Third Harmonic Distortion fIN = 10.3 MHz fIN = 82 MHz fIN = 160 MHz Spurious Free Dynamic Range (SFDR) fIN = 10.3 MHz fIN = 82 MHz fIN = 160 MHz Two-Tone Intermod Distortion IMD1 fIN1 = 80.3 MHz, fIN2 = 81.3 MHz
NOTES 1 IN1, IN2 level = -7 dBFS. Specifications subject to change without notice.
51 50 8.3 8.1 -56 -55 -58 -57 56 54
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AD9410
SAMPLE N-1 SAMPLE N SAMPLE N+3
SAMPLE N+4
SAMPLE N+5
AIN
SAMPLE N-2
tA
SAMPLE N+1 1/fS SAMPLE N+2 SAMPLE N+6
tEH tEL
ENCODE
ENCODE
tHDS tSDS
DS
DS
INTERLEAVED DATA OUT
INVALID INVALID INVALID
tPD
tV
DATA N+1 DATA N+3
Figure 1. Timing Diagram
-4-
INVALID INVALID INVALID
PORT A D7 D0
STATIC
PORT B D7 D0
STATIC
DATA N
DATA N+2
PARALLEL DATA OUT
INVALID INVALID INVALID INVALID DATA N+1
PORT A D7 D0
STATIC
PORT B D7 D0 INVALID
STATIC
INVALID
INVALID
DATA N
DATA N+2
tCPD
DCO
STATIC
DCO
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AD9410
ABSOLUTE MAXIMUM RATINGS 1
VD, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VCC + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VDD + 0.5 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature2 . . . . . . . . . . . . . . . . 150C
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. 2 Typical JA = 22C/W (heat slug not soldered), typical JA = 16C/W (heat slug soldered), for multilayer board in still air with solid ground plane.
EXPLANATION OF TEST LEVELS Test Level
I.
100% production tested.
II. 100% production tested at 25C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range.
ORDERING GUIDE
Model AD9410BSQ AD9410/PCB
Temperature Range -40C to +85C 25C
Package Description PowerQuad 2 Evaluation Board
Package Option SQ-80
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9410 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD9410
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24, 27, 28, 29, 30, 71, 72, 73, 74, 77, 78 3, 7, 14, 15 4 5 6 10 11 18 19 22 23 25, 26, 31, 32, 69, 70, 75, 76 33, 40, 49, 52, 59, 68 34, 41, 48, 53, 60, 67 35-39 42-46 47 50 51 54-58 61-65 66 79 80
Mnemonic AGND VCC REFOUT REFIN DNC AIN AIN ENCODE ENCODE DS DS VD DGND VDD DB0-DB4 DB5-DB9 ORB DCO DCO DA0-DA4 DA5 -DA9 ORA DFS I/P
Function Analog Ground. 5 V Supply. (Regulate to within 5%.) Internal Reference Output. Internal Reference Input. Do Not Connect. Analog Input--True. Analog Input--Complement. Clock Input--True. Clock Input--Complement. Data Sync (Input)--True. Tie LOW if not used. Data Sync (Input)--Complement. Float and decouple with 0.1 F capacitor if not used. 3.3 V Analog Supply. (Regulate to within 5%.) Digital Ground. 3.3 V Digital Output Supply. (2.5 V to 3.6 V) Digital Data Output for Channel B. (LSB = DB0.) Digital Data Output for Channel B. (MSB = DB9.) Data Overrange for Channel B. Clock Output--Complement. Clock Output--True. Digital Data Output for Channel A. (LSB = DA0.) Digital Data Output for Channel A. (MSB = DA9.) Data Overrange for Channel A. Data Format Select. HIGH = Two's Complement, LOW = Binary. Interleaved or Parallel Output Mode. Low = Parallel Mode, High = Interleaved Mode. If tying high, use a current limiting series resistor (2.5 k) to the 5 V supply.
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AD9410
PIN CONFIGURATION
DA9 (MSB)
AGND
AGND
AGND
AGND
AGND
AGND
DGND
ORA
DFS
VDD
DA8
DA7
DA6
62
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
61
DA5
VD
VD
VD
VD
I/P
AGND 1 AGND 2 VCC 3 REFOUT 4 REFIN 5 DNC 6 VCC 7 AGND 8 AGND 9 AIN 10 AIN 11 AGND 12 AGND 13 VCC 14 VCC 15 AGND 16 AGND 17 ENCODE 18 ENCODE 19 AGND 20
60 PIN 1 IDENTIFIER 59 58 57 56 55 54 53 52
VDD DGND DA4 DA3 DA2 DA1 DA0 (LSB) VDD DGND DCO DCO DGND VDD ORB DB9 (MSB) DB8 DB7 DB6 DB5 VDD
AD9410
TOP VIEW 80-Lead PowerQuad2 (Not to Scale)
51 50 49 48 47 46 45 44 43 42 41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DS
AGND
DS
AGND
AGND
AGND
AGND
AGND
DGND
DNC
DO NOT CONNECT
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-7-
(LSB) DB0
DGND
VDD
VD
VD
VD
VD
DB1
DB2
DB3
DB4
AD9410
DEFINITIONS OF SPECIFICATIONS Analog Bandwidth Minimum Conversion Rate
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The encode rate at which parametric testing is performed.
Output Propagation Delay
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels.
Out-of-Range Recovery Time
The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer.
Differential Analog Input Voltage Range
Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
Noise (For Any Range Within the ADC)
FSdBm - SIGNALdBFS 10
The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. The difference is then computed between both peak measurements.
Differential Nonlinearity
VNOISE = | Z | x0.001 x 10
Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level, and SIGNAL is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.
Power Supply Rejection Ratio
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The effective number of bits (ENOB) is calculated from the measured SINAD based on the equation.
Full Scale Amplitude SINADMEASURED - 1.76 dB + 20 log Input Amplitude ENOB = 6.02
The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc.
Signal-to-Noise Ratio (Without Harmonics)
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specs define an acceptable ENCODE duty cycle.
Full-Scale Input Power
The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale).
Transient Response Time
Expressed in dBm. Computed using the following equation:
POWERFULL SCALE
V 2 FULL SCALErms Z INPUT = 10 log 0.001

Transient response time is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc.
Integral Nonlinearity
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale).
Worst Other Spur
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least-square curve fit. -8-
The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. REV. 0
AD9410
Table I. Output Coding (VREF = 2.5 V)
Step 1023 * * 513 512 511 * * 0
AIN-AIN > 0.768 0.768 * * 0.0015 0.0 -0.0015 * * -0.768 < -0.768
Digital Outputs Offset Binary 11 1111 1111 11 1111 1111 * * 10 0000 0001 10 0000 0000 01 1111 1111 * * 00 0000 0000 00 0000 0000
Digital Outputs Two's Complement 01 1111 1111 01 1111 1111 * * 00 0000 0001 00 0000 0000 11 1111 1111 * * 10 0000 0000 10 0000 0000
ORA, ORB 1 0 * * 0 0 0 * * 0 1
VCC
VCC
1.5k AIN
1.5k AIN
VREFOUT
2.25k
2.25k
Figure 6. Equivalent Reference Output Circuit Figure 2. Equivalent Analog Input Circuit
VCC
VCC
DFS 100k
VREFIN
Figure 7. Equivalent DFS Input Circuit Figure 3. Equivalent Reference Input Circuit
VCC
VCC 17.5k 300 DS 300 DS
17k ENCODE
450
450
17k ENCODE
7.5k
100 8k
100 8k
Figure 8. Equivalent DS Input Circuit Figure 4 Equivalent Encode Input Circuit
17.5k
VDD
VCC 300 I/P
DIGITAL OUTPUT
7.5k
Figure 5. Equivalent Digital Output Circuit
Figure 9. Equivalent I/P Input Circuit
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AD9410 -Typical Performance Characteristics
0 ENCODE = 210MSPS AIN = 40MHz @ -0.5dBFS SNR = 54.5dB SINAD = 53.5dB
55 54 53 SNR 52
-20
-40
51
dB
dB
-60
50 49
-80
48 47
SINAD
-100
46
-120 0 MHz 105
45 0 50 100 150 AIN - MHz 200 250
TPC 1. Single Tone at 40 MHz, Encode = 210 MSPS
TPC 4. SNR/SINAD vs. AIN Encode = 210 MSPS
0 ENCODE = 210MSPS AIN = 100MHz @ -0.5dBFS SNR = 53.5dB SINAD = 52.5dB
55.0 54.5 SNR 54.0 53.5 53.0
-20
-40
dB
-60
dB
52.5 SINAD 52.0
-80 51.5 -100 51.0 50.5 -120 0 MHz 105 50.0 100 120 140 160 MHz 180 200 220 240
TPC 2. Single Tone at 100 MHz, Encode = 210 MSPS
TPC 5. SNR/SINAD vs. FS AIN = 70 MHz
0 ENCODE = 210MSPS AIN = 160MHz @ -0.5dBFS SNR = 53dB SINAD = 52dB
60
-20
55
SNR SINAD
-40
50
dB
-60
dB
45
-80
40
-100
35
-120 0 MHz 105
30
0
0.5
1.0
1.5
2.0 ns
2.5
3.0
3.5
4.0
TPC 3. Single Tone at 160 MHz, Encode = 210 MSPS
TPC 6. SNR/SINAD vs. Encode Positive Pulsewidth (FS = 210 MSPS, AIN = 70 MHz)
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AD9410
0 -20 ENCODE = 210MSPS AIN1, AIN2 = -7dBFS SFDR = 62dBFS 2.52 2.51
-40
VOLTS
2.50
dB
-60
2.49
-80
2.48
-100
2.47
-120 0 MHz 105
2.46 4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
ANALOG SUPPLY
TPC 7. Two Tone Test AIN 1 = 80.3 MHz, AIN 2 = 81.3 MHz
TPC 10. VREFOUT vs. Analog 5 V Supply
55.5 55.0 54.5 54.0 SNR
dB
460 410 360 310 260
mA
IAhi3
53.5 53.0
210 160 52.5 SINAD 52.0 51.5 -40 60 Ivdd -20 0 20 40 60 80 100 120 10 100 120 140 160 MSPS 180 200 220 110
IAhi5
TEMPERATURE - C
TPC 8. SNR/SINAD vs. Temperature, Encode = 210 MSPS, AIN = 70 MHz
TPC 11. Power Supply Currents vs. Encode
74 72 H2 70 68 66 H3 64
VOLTS
2.55
2.50
2.45
dB
2.40
2.35
62
2.30
60 58 -40
2.25
-20
0
20
40
60
80
100
120
0
0.5
1.0 mA
1.5
2.0
2.5
TEMPERATURE - C
TPC 9. Second and Third Harmonics vs. Temperature; AIN = 70 MHz, Encode = 210 MSPS
TPC 12. VREFOUT vs. ILOAD
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AD9410
2.503 2.502 2.501
5.1 TPD 4.9 TV
4.7
VOLTS
2.500
ns
2.499
4.5 TCPD 4.3
2.498
2.497 2.496 -40
4.1
-20
0
20 40 TEMPERATURE - C
60
80
3.9 -40
-20
0
20 40 TEMPERATURE - C
60
80
TPC 13. VREFOUT vs. Temperature
TPC 14. TPD, TV, TCPD vs. Temperature
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AD9410
APPLICATION NOTES
THEORY OF OPERATION Analog Input
The AD9410 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the flash 10-bit core. For ease of use the part includes an onboard reference and input logic that accepts TTL, CMOS, or PECL levels.
USING THE AD9410 ENCODE Input
VOLTS
Any high-speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A Track/Hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9410, and the user is advised to give commensurate thought to the clock source. To limit SNR degradation to less than 1 dB, a clock source with less than 1.25 ps rms jitter is required for sampling at Nyquist. (Valpey Fisher VF561 is an example.) Note that required jitter accuracy is a function of input frequency and amplitude. Consult Analog Devices' application note AN-501, "Aperture Uncertainty and ADC System Performance," for more information. The ENCODE input is fully TTL/CMOS-compatible. The clock input can be driven differentially or with a single-ended signal. Best performance will be obtained when driving the clock differentially. Both ENCODE inputs are self-biased to 1/3 x VCC by a high impedance resistor divider. (See Equivalent Circuits section.) Single-ended clocking, which may be appropriate for lower frequency or nondemanding applications, is accomplished by driving the ENCODE input directly and placing a 0.1 F capacitor at ENCODE.
The analog input to the AD9410 is a differential buffer. For best dynamic performance, impedances at AIN and AIN should match. The analog input has been optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance will degrade significantly if the analog input is driven with a single-ended signal. A wideband transformer such as Minicircuits ADT1-1WT can be used to provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 3 V. (See Equivalent Circuits section.) Special care was taken in the design of the Analog Input section of the AD9410 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.5 V diff p-p. The nominal differential input range is 768 mV p-p x 2.
3.384
AIN
3.000
2.616
AIN
Figure 12. Typical Analog Input Levels
Digital Outputs
TTL/CMOS GATE
AD9410 ENCODE
ENCODE
0.1 F
Figure 10. Driving Single-Ended Encode Input at TTL/CMOS Levels
An example where the clock is obtained from a PECL driver is shown in Figure 11. Note that the PECL driver is ac-coupled to the ENCODE inputs to minimize input current loading. The AD9410 can be dc-coupled to PECL logic levels resulting in the ENCODE input currents increasing to approximately 8 mA typically. This is due to the difference in dc bias between the ENCODE inputs and a PECL driver. (See Equivalent Circuits section.)
0.1 F ENCODE PECL GATE 510 GND 510 0.1 F ENCODE
The digital outputs are TTL/CMOS-compatible for lower power consumption. The outputs are biased from a separate supply (VDD), allowing easy interface to external logic. The outputs are CMOS devices which will swing from ground to VDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (<1 inch, for a total CLOAD < 5 pF). It is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance.
Clock Outputs (DCO, DCO)
AD9410
The input ENCODE is divided by two and available off-chip at DCO and DCO. These clocks can facilitate latching off-chip, providing a low skew clocking solution (see timing diagram). These clocks can also be used in multiple AD9410 systems to synchronize the ADCs. Depending on application, DCO or DCO can be buffered and used to drive the DS inputs on a second AD9410, ensuring synchronization. The on-chip clock buffers should not drive more than 5 pF-7 pF of capacitance to limit switching transient effects on performance.
Voltage Reference
Figure 11. Driving the Encode Inputs Differentially
A stable and accurate 2.5 V voltage reference is built into the AD9410 (VREF OUT). The input range can be adjusted by varying the reference voltage. No appreciable degradation in performance occurs when the reference is adjusted 5%. The fullscale range of the ADC tracks reference voltage changes linearly within the 5% tolerance. -13-
REV. 0
AD9410
Timing Data Sync (DS)
The AD9410 provides latched data outputs, with six pipeline delays in interleaved mode (see Figure 1). In parallel mode, the A Port has one additional cycle of latency added on-chip to line up transitions at the data ports--resulting in a latency of seven cycles for the A Port. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9410; these transients can detract from the converter's dynamic performance. The minimum guaranteed conversion rate of the AD9410 is 100 MSPS. At internal clock rates below 100 MSPS, dynamic performance may degrade. Note that lower effective sampling rates can be obtained simply by sampling just one output port-- decimating the output by two. Lower sampling frequencies can also be accommodated by restricting the duty cycle of the clock such that the clock high pulsewidth is a maximum of 5 ns.
The Data Sync input, DS, can be used in applications requiring that a given sample will appear at a specific output Port A or B. When DS is held high, the ADC data outputs and clock do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS, within the timing constraints TSDS and THDS relative to an encode rising edge. (On initial synchronization THDS is not relevant.) If DS falls within the required setup time (TSDS) before a given encode rising edge N, the analog value at that point in time will be digitized and available at Port B six cycles later (interleaved mode). The very next sample, N+1, will be sampled by the next rising encode edge and available at Port A six cycles after that encode edge (interleaved mode). In dual parallel mode the A Port has a seven cycle latency, the B Port has a six cycle latency, but data is available at the same time.
EVALUATION BOARD
REFERENCE
The AD9410 evaluation board offers an easy way to test the AD9410. The board requires an analog input, clock, and 3 V, 5 V power supplies. The digital outputs and output clocks are available at a standard 80-lead header P2, P3. The board has several different modes of operation, and is shipped in the following configuration:
The AD9410 has an on-chip reference of 2.5 V available at REFOUT (Pin 4). Most applications will simply tie this output to the REFIN input (Pin 5). This is accomplished by placing a jumper at E1, E6. An external reference can be used placing a jumper at E1, E3.
Output Timing
* Output Timing = Parallel Mode * Output Format = Offset Binary * Internal Voltage Reference
Power Connector
The chip has two timing modes (see timing diagram). Interleaved mode is selected by Jumper E11, E7. Parallel mode is selected by Jumper E11, E14.
Data Format Select
Power is supplied to the board via detachable 4-pin power strips P1, P4, P5. VDAC - Optional DAC Supply Input (3.3 V) EXT REF - Optional External VREF Input (2.5 V) VDD - Logic Supply (3.3 V) 3.3 VA - Analog Supply (3.3 V) 5 V - Analog Supply (5 V)
Analog Inputs
Data Format Select sets the output data format that the ADC outputs. Setting DFS (Pin 79) low at E12, E10 sets the output format to be offset binary; setting DFS high at E12, E16 sets the output to be two's complement.
DS Pin
The DS, DS inputs are available at SMB connectors J9X and J10X. The board is shipped with DS pulled to ground by R26. DS is floating (R25X is not placed).
DAC Outputs
The evaluation board accepts a 1.5 V p-p analog input signal centered at ground at SMB J8. This input is terminated to 50 on the board at the transformer secondary, but can be terminated at the SMB if an alternative termination is desired. The input is ac-coupled prior to the transformer. The transformer is band limited to frequencies between approximately 1 MHz and 400 MHz.
Encode
Each channel is reconstructed by an on-board dual channel DAC, an AD9751 to assist in debug. The performance of the DAC has not been optimized and will not give an accurate measure of the full performance of the ADC. It is a current output DAC with on-board 50 termination resistors. The outputs are available at J3 and J4.
The encode input to the board is at SMB connector J1. The input is terminated on the board with 50 to ground. The (>0.5 V p-p) input is ac-coupled and drives a high-speed differential line receiver (MC10EL16). This receiver provides sub- nanosecond rise times at its outputs--a requirement for the ADC clock inputs for optimum performance. The EL16 outputs are PECL levels and are ac-coupled to meet the commonmode dc levels at the AD9410 encode inputs.
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REV. 0
AD9410
GND
GND C1 10 F 5V C2 10 F C3 10 F VDD C5 10 F C4 10 F J1 R19 8.2k C6 0.1 F 5V 5V R14 8.2k GND MC10EL16
1 2
C40 0.1 F 5V
3.3VA
EXT REF
VDAC
NC D D VBB U1
VCC 8 Q
7
R11 330
C7 0.1 F ENCT ENCC
1 2
VDAC GND EXT REF GND GND GND VDD/3.3V GND E10 R6 100 GND 5V
GND
R8 50 GND
3
Q6 VEE 5 GND R15 330 GND C8 0.1 F
R18 24k
R9 24k
4
P4
3 4 1 2
GND GND VDD 3.3VA R4 2.5k GND E16 E12 E7 E11 E14 GND GND C27 0.1 F GND
1 2 3 4 5 80 79 78
P1
3 4 1 2
C10 0.1 F GND
3.3VA
C14 0.1 F GND DA9 DA8 DA7 NOTE: R3, R6, R7, R24 OPTIONAL (CAN BE ZERO ) DA6 DA5
64 63 62 61
3.3VA GND 5V GND GND 5V
R24 100 R3 100
R7 100 3.3VA GND
77 76 75
C11 0.1 F GND GND 3.3VA GND
74 73 72 71 70 69 68
P5
3 4
DAOR
67 66 65
GND C12 0.1 F VDD 60 VDD GND DA4 DA3 DA2 DA1 DA0 VDD C21 0.1 F GND
DFS
I/P
AGND
AGND
AGND
AGND
AGND
AGND
DGND
ORA
VD
VD
VD
VD
VDD
DA9
DA8
DA7
DA6
AGND AGND VCC REFOUT REFIN DNC VCC AGND AGND AIN AIN AGND AGND VCC VCC AGND AGND ENCODE ENCODE
DA5
DGND 59 DA4 58 DA3 57 DA2 56 DA1 55 DA0 54 VDD 53 DGND 52
GND E6 EXT REF E3 E1 5V C28 0.1 F
5V
6 7
C26 0.1 F GND GND
8 9 10
J8
GND C7 0.1 F AIN
1 2 3
T1
6 5 4
GND DCOT DCOC GND
R27 50 GND GND C24 0.1 F GND 5V GND
11 12 13 14 15 16 17
AD9410 U3
DCO 51 DCO 50 DGND 49 VDD 48 ORB 47 DB9 46 DB8 45 DB7 44 DB6 43 DB5 42
1:1 R23 50 C25 0.1 F GND GND
GND
DBOR DB9 DB8 DB7 DB6 DB5 VDD C18 0.1 F GND
VDD C22 0.1 F GND
ENCT ENCC GND
18 19 20
AGND
AGND
AGND
AGND
AGND
DGND
AGND
DS
DS
VD
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
J9X
GND R26 50 GND J10X
GND GND C15 0.1 F
3.3VA
GND
DB0 DB1 DB2 DB3 C19 0.1 F VDD DB4 GND
3.3VA GND
R25X 50 GND
3.3VA GND
C16 3.3VA 0.1 F
Figure 13a. PCB Schematic
REV. 0
-15-
DGND
AGND
VDD 41
VDD
DB0
DB1
DB2
DB3
DB4
VD
VD
VD
40
39 37
GND DRA GND DM9 DM8 DM7 DM6
RPACK
38 36 35 33 31 29 27 25 23 21
AD9410
RPACK
1 1A
1B 16 2B 15
34 32 30 28 26 24 22 20 18
DAOR DA9
2 2A 3 3A
1 1A
1B 16 2B 15 3B 14 DX8 74LCXB21 GND D5A D4A D3A
8 8A 7 7A 6 6A 1 DE
DXOR DX9 D7A
4 4A
D9A GND D8A
3 3A
2 2A
DM9 DM8 DM7 DM6 DM5 DM4 DM3
3B 14
DA8 DA7
4 4A
R34
5B 12 6B 11 7B 10 8B 9
4B 13
R32
VCC 24 Y0 23 Y1 22 Y2 21 Y3 20 D6A D5A D4A D3A D2A D1A D0A CLKA NC NC NC
6 6A 7 7A 8 8A
4B 13 DX7 DX6 DX9
2 X0 3 X1 4 X2 5 X3 6 X4
C37 0.1 F VDD D6A
5 5A
DA6 D9A D8A D7A DA5 DX8 DX7 DX6 DX5 DA4 DX4 DX3 DA3
8 8A 7 7A 6 6A
5 5A
5B 12 6B 11 DX5 7B 10 8B 9
DM5 DM4 DM3
VDD
P2
19 17 16 15 14 13
DM2 DM1 DM0 GND
C32 0.1 F DX4
7 X5 8 X6 9 X7 10 X8 11 X9 12 GND
U4
Y5 18 Y6 17 Y7 16 Y8 15 Y9 14 CLK 13 NC
5 5A
Y4 19 RPACK D2A
1 1A 2 2A 3 3A 4 4A
RPACK DX3 DX2 DX1 DX0 DX0 GND NC DX1 D0A 3B 14 4B 13 5B 12 6B 11 7B 10 8B 9 DX2 D1A 2B 15 DA2
1 1A 2 2A 3 3A
1B 16
DM2 DM1 DM0 NC NC NC NC NC GND
GND 1B 16 2B 15 3B 14 DA1 DA0
4 4A
12 10 8 6 4 2
11 9 7 5 3 1
GND GND GND GND GND GND HEADER 40
DCOT
DCOTA
R36
R16 00
R40
5B 12 6B 11 7B 10 8B 9
4B 13
DCOC
6 6A 7 7A 8 8A
R17 00
DCOCA
5 5A
Figure 13b. PCB Schematic (Continued)
RPACK RPACK
1 1A 2 2A 3 3A 4 4A
-16-
1B 16 2B 15 3B 14 GND 74LCXB21 GND DYOR DY9 DY8 DY7 DY6 CLKA RPACK DB7 DB6
2 2A 3 3A 4 4A 5 5A 6 6A 7 7A 1 1A 1 DE 2 X0 3 X1 4 X2 5 X3
40 38
39 37
GND DRB NC NC NC NC
1 1A 2 2A 3 3A 4 4A
1B 16 2B 15 3B 14
NC NC NC
36 34 32
35 33 31
GND DN9 DN8 4B 13 NC
VDD
R29
5B 12 6B 11 7B 10 8B 9 DY8 DY9
4B 13
R28
C39 0.1 F VCC 24 Y0 23 Y1 22 Y2 21 VDD D9B D8B D7B D9B D8B NC
5 5A 6 6A 7 7A 8 8A
30
29
DN7 5B 12 6B 11 7B 10 8B 9 DN9 DN8 NC
28 26 24 22 20 27 25 23 21
DN6 DN5 DN4 DN3
E24
E17 DRA DB9 DB8 6
8 8A 7 7A
R2 100
1
E18
XORA
DCOTA XORA
2
U9
R44 3 00 DBOR
6 6A
5 5A
GND
74AC86
P3
DY5 DY4
6 X4 7 X5
19
VDD
DN2
DCOTA
R37 E26 100 E27 XORB E28
XORB
4 5
U9
U5
Y3 20 Y4 19 Y5 18
D6B D5B D4B D7B D6B RPACK
1 1A
18 16
17 15
DN1 DN0 1B 16 DN7
14 13
GND
74AC86
1B 16 2B 15 3B 14 4B 13
GND DY7 DY6 DY5 DY4 DY3 DY2 DY1
8 X6 9 X7 10 X8
VDD
Y6 17 Y7 16 Y8 15
D3B D2B D1B
2 2A
2B 15 D5B D4B
3 3A 4 4A
DN6 3B 14 DN5
R42 E20 100 E19 XORC E21
DCOCA XORC
12 13
U9
DRB DB5 DB4 DB3
R45 11 00
12 10
11 9
GND GND 4B 13 DN4
GND
74AC86
R38 R39
DY0 5B 12 6B 11 7B 10 DY3 DY2 DY1 GND
11 X9 12 GND
8
7
GND Y9 14 CLK 13 D0B CLKB D3B D2B D1B D0B
5 5A 6 6A 7 7A 8 8A
5B 12 6B 11 7B 10 8B 9
DN3 DN2 DN1 DN0
6 4 2 5 3 1
GND GND GND
VDD
E23 R43 100 E25 XORD E22
DCOTA XORD
9 10
U9
CLKB
8
DB2 DB1 DB0
REV. 0
GND
74AC86
8 8A
8B 9
DY0 GND
HEADER 40
AD9410
J3 R1 50 GND J4 GND R12 50 R5 392 GND GND C33 1F R13 392 GND GND
48 47 46 45 44 43 42 41 40 39 38 37
GND C3 0.1 F VDAC R10 2k GND
C23 0.1 F GND E2
VDAC
VDAC E4 GND VDAC E29 GND
E5 E31 E30
VDAC C20 0.1 F GND
VDAC E34 GND
E32
1 36 35 34 33 32
E33
DCOCA DCOTA GND
2 3 4 5
VDAC C13 0.1 F GND E35 DM9 DM8 DM7 DM6 DM5 DM4
DN0 DN1 DN2 DN3 DN4 DN5 DN6 DN7
6 7 8 9 10 11 12
AD9751 U2
31 30 29 28 27 26 25
13
14
15
16
17
18
19
20
21
22
23
24
DM3
DM2
DM1 DM0 C17 0.1 F GND
GND DN9
DN8
VDAC
Figure 13c. PCB Schematic (Continued)
TROUBLESHOOTING
If the board does not seem to be working correctly, try the following:
* Try running encode clock and analog input at low speeds (10 MSPS/1 MHz) and monitor latch outputs, DAC outputs, and ADC outputs for toggling. The AD9410 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
* Verify power at IC pins. * Check that all jumpers are in the correct position for the
desired mode of operation.
* Verify VREF is at 2.5 V.
REV. 0
-17-
AD9410
EVALUATION BOARD LAYOUT
Figure 14. Top Silkscreen
Figure 17. Bottom Components and Routing
Figure 15. Split Power Plane
Figure 18. Bottom Silkscreen
Figure 16. Ground Plane
Figure 19. Top Components and Routing
-18-
REV. 0
AD9410
AD9410 Evaluation Board Bill of Material
Quantity 5 29 1 31 6 3 2 7 8 1 1 2 1 2 2 5 8 1 1 1 1 2 1
Reference Description C1-C5 C6-C30, C32, C37, C39, C40 C33 E1-E7, E10-E12, E14, E16-E35 J1, J3, J4, J8, J9X, J10X P1, P4, P5 P2, P3 R1, R8, R12, R23*, R25X, R26, R27 R2, R3, R4, R6, R24, R37, R42, R43 R13 R7 R9, R18 R10 R11, R15 R14, R19 R5, R16, R17, R44, R45 R28, R29, R32, R34, R36, R38-R40 T1 U1 U2 U3 U4, U5 U9
Device Capacitor Capacitor Capacitor Ehole SMB 4-Pin Power Connector 40-Pin Header Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor RPACK Transformer (1:1) MC10EL16 AD9751 AD9410 74LCX821 74AC86
Package TAJD 603 1206
Value 10 F 0.1 F 1 F Wieland 50 100 392 100 24 k 2 k 330 8.2 k 0 CTS Minicircuits
25.531.3425.0 25.602.5453.0 1206 1206 1206 1206 1206 1206 1206 1206 1206 766163220G 22 ADT1-1WT SOIC8 LQFP48 LQFP80 SOIC24 SOIC14
*Optional R23 not placed on board (50 termination resistor).
REV. 0
-19-
AD9410
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead PowerQuad 2 (LQFP_ED) (SQ-80)
0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) SEATING PLANE
80 1
0.551 (14.00) SQ
61 60 60 61 80
0.120 (3.04) 4 PLACES
45 C CHAMFER
1
PIN 1
TOP VIEW
(PINS DOWN)
BOTTOM VIEW NICKEL PLATED
0.413 (10.50) 0.394 (10.00) REF 0.374 (9.50)
XX
COPLANARITY 0.004 (0.10) MAX 0.006 (0.15) 0.002 (0.05)
20 21 40 41 41 40 21 20
0.057 (1.45) 0.055 (1.40) 0.053 (1.35)
0.413 (10.50) 0.394 (10.00) REF 0.374 (9.50) CONTROLLING DIMENSION IN MILLIMETERS. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
0.008 (0.20) 0.004 (0.09)
0.0256 (0.65) BSC
0.015 (0.38) 0.013 (0.32) 0.009 (0.22)
7 0
NOTE The AD9410 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. The slug is exposed on the bottom of the package. It is recommended that no PCB traces or vias be located under the package that could come in contact with the conductive slug. Attaching the slug to a ground plane while not required in most applications will reduce the junction temperature of the device which may be beneficial in high temperature environments.
-20-
REV. 0
PRINTED IN U.S.A.
C01679-4.5-10/00 (rev. 0)
0.630 (16.00) SQ

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